Conventionally, an integrated circuit device can be connected, only by the input-output characteristics thereof being guaranteed, to another integrated circuit device such that the devices function as a communication system in which one of the devices serves as a transmitter and the other serves as a receiver. However, the frequency of an interface signal between integrated circuit devices has reached a range exceeding 200 MHz to 400 MHz, and therefore, the difference in timing between different signals has posed a problem. In particular, some difference in timing between a clock signal and a data signal which is transmitted in synchronization with the clock signal or some difference in timing between data signals may lead to a situation that a data signal cannot be correctly captured.
To address such a problem, for example, a SerDes (SERializer/DESerializer) etc. may be used in which a clock signal and a data signal are superimposed on a single line using an algorithm, and transmit and receive the resultant signal.
Also, for example, Patent Literature 1 discloses a data transmission circuit in which a skew between data signals is reduced to the extent possible. Specifically, in the data transmission circuit, the drive ability at a transmitter side is modified to eliminate or minimize the time difference between a reception timing and a predetermined intended timing when a predetermined signal is transmitted over each of a first transmission path and a second transmission path.